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METHODOLOGIES FOR BUILT-IN SELF-TEST INSERTION IN VLSI CIRCUITS ACROSS THE DESIGN HIERARCHY
Carletta, Joan E.
CASE WESTERN RESERVE UNIV CLEVELAND OHDEPT OF COMPUTER ENGINEERING AND SCIENCE
Methodologies for Built In Self Test (BIST) insertion in VLSI circuits are presented for three different levels of design abstraction. The methodologies are designed to be used during the design flow of Application Specific Integrated Circuits (ASICs), which starts at the algorithmic level in the behavioral domain and moves to the register transfer level in the structural domain, and finally to the gate level in the structural domain. At each level, the methodology is based on the use of testability metrics to identify and remove points of low testability in a circuit. By quantifying the properties that make a BIST scheme successful, the testability metrics provide a way to measure test quality implicitly, without resorting to fault simulation, which is both expensive and not available at the higher levels of design abstraction. The testability metrics are computed using a Markov chain model. Fault coverage curves show that when the BIST insertion methodologies are applied, the resulting circuits are significantly easier to test than circuits designed without regard to testability. Wherever fault coverage results are given, layout areas, transistor counts, and critical delays are also given so that the trade- off between a circuit's testability and its area and performance can be fully appreciated. Examples of our insertion methodologies employ three different BIST schemes: conventional BIST, circular BIST, and the circular self-test path technique. For circular BIST and the circular self-test path technique, special care must be taken when adding the test circuitry to a design. This work explores the problems that can occur, and outlines structural constraints that should be followed to avoid the problems.
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